The growing demand for matrix multiplication in artificial intelligence must be met with increased tensor computing efficiency and bandwidth improvements. While AI throughput using digital hardware accelerators has advanced, the potential of analog circuits has been largely untapped. In this paper, we introduce a novel Fourier-Accelerated CMOS-based Tensor Engine (FATE) that aims to optimize the high complexity of matrix multiplication with computation and bandwidth efficiencies. First, our design reduces the computational complexity of matrix multiplication from the traditional O($N^3$) to O($N^3$/f), where f is a number of frequency carriers up to N. Second, our circuit dramatically reduces the bandwidth required for moving vectors by encoding a vector as a summed sine series routed via two physical wires. The test circuit, designed with a 180 nm standard CMOS process, achieves a strong dot product linearity with an $R^2$ value of 0.94. This work highlights the untapped potential of analog circuits in modern AI, offering a highly efficient solution to a critical bottleneck in AI computation.
Index Item: Machine Learning, Artificial Intelligence, Accelerators, Neural Networks, Analog Circuits, Fourier Series, Matrix Multiplication, Dot Product
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